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| New Circuit and Structures for Combinational Multipliers | ||
| 作者 | Song, Paul Jei-zen |
|---|---|
| 出版日期 | 1993 |
| 出版者 | Stanford University |
| 出版者網址 | https://www.stanford.edu |
| 出版地 | Stanford, CA, US [史丹佛, 加利福尼亞州, 美國] |
| 資料類型 | 博碩士論文=Thesis and Dissertation |
| 使用語言 | 英文=English |
| 學位類別 | 博士 |
| 校院名稱 | Stanford University |
| 系所名稱 | Department of Electrical Engineering |
| 指導教授 | DeMicheli, Giovanni |
| 畢業年度 | 1993 |
| 附註項 | 450 |
| 摘要 | A critical component of parallel multipliers is the partial-product reduction array. Wallace proposed a scheme for implementing this array by using of carry-save adders. His scheme, when applied to IEEE-standard double-precision floating-point multiplication, requires nine stages of counters that can be reduced to seven by using the modified Booth's algorithm. Unfortunately, Wallace trees lack regularity and may lead to irregular layouts, with significant long wires and associated delays. Other regular implementations, for example using (4,2) counters, require more stage delays. A new scheme is introduced that uses a new family of counters, called the (9,2) counter family. This family exploits hierarchical compositions of (3,2) counters. This scheme has the same number of stage delays as Wallace's, but it leads to more regular layouts. Therefore, it can support faster operation. In addition, it is amenable to computer-aided synthesis and optimization. Parameterized module generators in the L language have been used in the design for counters and the partial-product reduction array. These generators were used to synthesize the layout and to explore the scaling trends in different processes for high-performance multiplication. Three test structures for IEEE-standard double-precision floating-point multipliers were fully designed and fabricated in BiCMOS technology. The circuits were successfully tested. The fastest chip achieved the product (53 bits) reduction in at most 7.2 nsec, measured on silicon. Scaling calculations suggest that the proposed architecture could be used to build complete multipliers (including the final addition stage, normalization and rounding) operating in about 15 nsec and without iteration. The method is competitive with other approaches implemented in existing commercial multiplier chips. |
| 點閱次數 | 136 |
| 建檔日期 | 2000.03.07 |
| 更新日期 | 2016.04.26 |
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